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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 6 4 5 7 8 Name VDDO GND CLK1, CLK0 VDD OE SEL0 Q Power Power Input Power Input Input Output Type Description Output supply pin. Power supply ground. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Core supply pin. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDDO = 3.465V VDDO = 2.625V VDDO = 1.89V Test Conditions Minimum Typical 4 51 51 18 19 19 15 Maximum Units pF k k pF pF pF
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs SEL0 0 1 Input Selected to Q CLK0 CLK1
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REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5%, 2.5V5% OR 1.8V5%,TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 1.6 Typical 3.3 3.3 2. 5 1.8 Maximum 3.465 3.465 2.625 2.0 40 5 Units V V V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 2.5V5% OR 1.8V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 1.6 Typical 2. 5 2. 5 1.8 Maximum 2.625 2.625 2.0 36 5 Units V V V A A
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK0, CLK1, SEL0 OE CLK0, CLK1, SEL0 OE Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDDO = 3.3V 5%; NOTE 1 VOH Output HighVoltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 5%; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 5%; NOTE 1 -5 -150 2.6 1.8 VDD - 0.3 0.5 0.45 0.35 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 5 Units V V V V A A A A V V V V V V
Input High Current
IIL
Input Low Current
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C
Symbol fMAX tpLH tpHL t sk(i) t sk(pp) t jit tR / tF odc Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical Maximum 250 2.0 2.0 2.4 2.5 36 2.7 2.9 160 490 0.18 200 45 700 55 Units MHz ns ns ps ps ps ps % dB
45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol fMAX tpLH tpHL t sk(i) t sk(pp) tjit tR / tF odc Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical Maximum 250 2.3 2.3 2.6 2.6 23 2. 9 2. 9 106 350 0.14 30 0 46 700 54 Units MHz ns ns ps ps ps ps % dB
45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C
Symbol fMAX tpLH tpHL t sk(i) t sk(pp) t j it tR / tF odc Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical Maximum 250 2.3 2.3 3.1 3.1 19 3.9 3.9 66 350 0.16 35 0 46 850 54 Units MHz ns ns ps ps ps ps % dB
45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol fMAX tpLH tpHL t sk(i) t sk(pp) t jit tR / tF odc Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical Maximum 250 2.2 2.2 2.7 2.7 28 3.2 3.2 123 400 0.22 30 0 45 700 55 Units MHz ns ns ps ps ps ps % dB
45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C
Symbol fMAX tpLH tpHL t sk(i) t sk(pp) t j it tR / tF odc Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical Maximum 250 2.1 2.1 3.1 3.1 19 4.1 4.2 73 350 0.19 35 0 45 85 0 55 Units MHz ns ns ps ps ps ps % dB
45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter (Random)
at 155.52MHz (12kHz - 20MHz) = 0.18ps (typical)
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V5%
1.25V5%
2.45%
0.9V5%
V DD VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V5%
-0.9V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V5% 0.9V5%
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
VDD VDDO
SCOPE
Qx
Part 1 Qx
V
DDO
2
LVCMOS
GND
Part 2 Qy
V
DDO
2 tsk(pp)
-0.9V5%
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
VDD
80% 20% tR
80% 20% tF
CLK0, CLK1
2 VDDO
Q
2 tpLH
Clock Outputs
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
CLKx
V
DDO
Q
tPD1
Q t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
CLKy
Q
tPD2
tsk(i) = tPD1 - tPD1
INPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS83052I is: 967
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REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX
FOR
8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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Integrated Circuit Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 8. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS83052AGI 052AI 8 lead TSSOP tube -40C to 85C ICS83052AGIT 052AI 8 lead TSSOP 2500 tape & reel -40C to 85C ICS83052AGILF TBD 8 lead "Lead-Free" TSSOP tube -40C to 85C ICS83052AGILFT TB D 8 lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83052AGI
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REV. A AUGUST 2, 2005

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